View CAT5221WI-00_4280945.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CAT5221
Dual Digitally Programmable Potentiometer (DPPTM) with 64 Taps and I2C Interface
FEATURES
Two linear-taper digitally programmable potentiometers 64 resistor taps per potentiometer End to end resistance 2.5k, 10k, 50k or 100k Potentiometer control and memory access via I2C interface Low wiper resistance, typically 80 Nonvolatile memory storage for up to four wiper settings for each potentiometer Automatic recall of saved wiper settings at power up 2.5 to 6.0 volt operation Standby current less than 1A 1,000,000 nonvolatile WRITE cycles 100 year nonvolatile memory data retention 20-lead SOIC and TSSOP packages Industrial temperature range
DESCRIPTION
The CAT5221 is two Digitally Programmable Potentiometers (DPPsTM) integrated with control logic and 16 bytes of NVRAM memory. Each DPP consists of a series of 63 resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 6-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 6-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or 2 any of the non-volatile data registers is via a I C serial bus. On power-up, the contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control register (WCR). The CAT5221 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications.
For Ordering Information details, see page 15.
PIN CONFIGURATION
SOIC 20 Lead (W) TSSOP 20 Lead (Y)
RW0 RL0 RH0 A0 A2 RW1 RL1 RH1 SDA GND 1 2 3 4 20 19 18 17 VCC NC NC NC A1 A3 SCL NC NC NC
FUNCTIONAL DIAGRAM
RH0 RH1
SCL SDA
I2C INTERFACE
WIPER CONTROL REGISTERS
RW0
5 CAT 16 6 5221 15 7 8 9 10 14 13 12 11
RW1 A0 A1 A2 A3
CONTROL LOGIC
NONVOLATILE DATA REGISTERS
RL0
RL1
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc. No. MD-2113 Rev. K
CAT5221 PIN DESCRIPTION
Pin (SOIC) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name RW0 RL0 RH0 A0 A2 RW1 RL1 RH1 SDA GND NC NC NC SCL A3 A1 NC NC NC VCC Function Wiper Terminal for Potentiometer 0 Low Reference Terminal for Potentiometer 0 High Reference Terminal for Potentiometer 0 Device Address, LSB Device Address Wiper Terminal for Potentiometer 1 Low Reference Terminal for Potentiometer 1 High Reference Terminal for Potentiometer 1 Serial Data Input/Output Ground No Connect No Connect No Connect Bus Serial Clock Device Address Device Address No Connect No Connect No Connect Supply Voltage
PIN DESCRIPTION
SCL: Serial Clock The CAT5221 serial clock input pin is used to clock all data transfers into or out of the device. SDA: Serial Data The CAT5221 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-Or'd with the other open drain or open collector outputs. A0, A1, A2, A3: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of sixteen devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5221. RH, RL: Resistor End Points The two sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW: Wiper The two RW pins are equivalent to the wiper terminal of a mechanical potentiometer.
DEVICE OPERATION
The CAT5221 is two resistor arrays integrated with I2C serial interface logic, two 6-bit wiper control registers and eight 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resis- tors are connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the I2C bus. Additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode.
Doc. No. MD-2113 Rev. K
2
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT5221
ABSOLUTE MAXIMUM RATINGS(1) Parameter Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to VSS(2) VCC with Respect to Ground Package Power Dissipation Capability (TA = 25C) Lead Soldering Temperature (10s) Wiper Current RECOMMENDED OPERATING CONDITIONS Vcc = +2.5V to +6V Parameter Operating Ambient Temperature (Industrial) Ratings -40 to +85 Units C Ratings -55 to +125 -65 to +150 -2.0 to +VCC +2.0 -2.0 to +7.0 1.0 300 12 Units C C V V W C mA
POTENTIOMETER CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter RPOT RPOT RPOT RPOT Potentiometer Resistance (-00) Potentiometer Resistance (-50) Potentiometer Resistance (-10) Potentiometer Resistance (-2.5) Potentiometer Resistance Tolerance RPOT Matching Power Rating Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (5) Relative Linearity (6) Temperature Coefficient of RPOT Ratiometric Temp. Coefficient Potentiometer Capacitances Frequency Response Test Conditions Min Typ 100 50 10 2.5 20 1 50 6 300 150 VCC Max Units k k k k % % mW mA nV/Hz 1 0.2 300 20 10/10/25 0.4 % LSB(7) LSB(7) ppm/C ppm/C pF MHz
25C, each pot IW = +3mA @ VCC =3V IW = +3mA @ VCC = 5V VSS = 0V (4) RW(n)(actual) - R(n)(expected) RW(n+1) - [RW(n)+LSB](8) (4) (4) (4) RPOT = 50k
(8)
IW RW RW VTERM VN
80 GND TBD 1.6
TCRPOT TCRATIO CH/CL/CW fc
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V. (4) This parameter is tested initially and after a design or process change that affects the parameter. (5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (7) LSB = RTOT / 63 or (RH - RL) / 63, single pot (8) n = 0, 1, 2, ..., 63
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
3
Doc. No. MD-2113 Rev. K
CAT5221
D.C. OPERATING CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter ICC ISB ILI ILO VIL VIH VOL1 Power Supply Current Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0V) IOL = 3 mA Test Conditions fSCL = 400kHz VIN = GND or VCC; SDA Open VIN = GND to VCC VOUT = GND to VCC -1 VCC x 0.7 Min Typ Max 1 1 10 10 VCC x 0.3 VCC + 1.0 0.4 Units mA A A A V V V
CAPACITANCE TA = 25C, f = 1.0MHz, VCC = 5V Symbol CI/O(1) CIN
(1)
Parameter Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, A3, SCL)
Test Conditions VI/O = 0V VIN = 0V
Min
Typ
Max 8 6
Units pF pF
A.C. CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol fSCL TI
(1)
Parameter Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SLC Low to SDA Data Out and ACK Out Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (For a Repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time
Min
Typ
Max 400 50 0.9
Units kHz ns s s s s s s ns ns
tAA tBUF
(1)
1.2 0.6 1.2 0.6 0.6 0 100 0.3 300 0.6 50
tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF
(1) (1)
s ns s ns
tSU:STO tDH
POWER UP TIMING (1) Over recommended operating conditions unless otherwise stated. Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min Typ Max 1 1 Units ms ms
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2113 Rev. K
4
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT5221
WRITE CYCLE LIMITS Over recommended operating conditions unless otherwise stated. Symbol tWR Parameter Write Cycle Time Min Typ Max 5 Units ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. RELIABILITY CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol NEND TDR VZAP ILTH
(1) (1) (1)
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
Min 1,000,000 100 2000 100
Typ
Max
Units Cycles/Byte Years Volts mA
(1)(2)
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Figure 1. Bus Timing
tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tDH tBUF tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT BYTE n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL START BIT
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
STOP BIT
5
Doc. No. MD-2113 Rev. K
CAT5221 SERIAL BUS PROTOCOL
The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5221 will be considered a slave device in all applications. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT5221 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 0101 for the CAT5221 (see Figure 5). The next four significant bits (A3, A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to sixteen devices may be individually addressed by the system. Typically, +5V and ground are hard-wired to these pins to establish the device's address. After the Master sends a START condition and the slave address byte, the CAT5221 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT5221 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT5221 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5221 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a START condition. The Master then sends the address Figure 4. Acknowledge Timing
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Doc. No. MD-2113 Rev. K
6
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT5221 WRITE OPERATION
In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of CAT5221. The instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the selected register. The CAT5221 acknowledges once more and the Master generates the STOP condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT5221 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address. If the CAT5221 is still busy with the write operation, no ACK will be returned. If the CAT5221 has completed the write operation, an ACK will be returned and the host can then proceed with the next instruction operation.
Figure 5. Slave Address Bits
CAT5221
0
1
0
1
A3
A2
A1
A0
*
A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Write Timing
S T A R T
S
BUS ACTIVITY: MASTER SDA LINE
SLAVE/DPP ADDRESS
Fixed Variable
INSTRUCTION BYTE
op code
Pot/WCR Data Register Address Address
DR WCR DATA
S T O P P
A C K
A C K
A C K
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
7
Doc. No. MD-2113 Rev. K
CAT5221 INSTRUCTIONS AND REGISTER DESCRIPTION
INSTRUCTIONS SLAVE ADDRESS BYTE The first byte sent to the CAT5221 from the master/ processor is called the Slave/DPP Address Byte. The most significant four bits of the slave address are a device type identifier. These bits for the CAT5221 are fixed at 0101[B] (refer to Table 1). The next four bits, A3 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 - A0 input pins for the CAT5221 to successfully continue the com- mand sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE The next byte sent to the CAT5221 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I [3:0]. The P0 bit points to one of the Wiper Control Registers. The least two significant bits, R1 and R0, point to one of the four data registers of each associated potentiometer. The format is shown in Table 2. Data Register Selection Data Register Selected DR0 DR1 DR2 DR3 R1 0 0 1 1 R0 0 1 0 1
Table 1. Identification Byte Format
Device Type Identifier
Slave Address
ID3 0 (MSB)
ID2 1
ID1 0
ID0 1
A3
A2
A1
A0 (LSB)
Table 2. Instruction Byte Format
Instruction Opcode Data Register Selection
WCR/Pot Selection
I3 (MSB)
I2
I1
I0
0
P0
R1
R0 (LSB)
Doc. No. MD-2113 Rev. K
8
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT5221 WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR) The CAT5221 contains two 6-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 64 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction, it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. The Wiper Control Register is a volatile register that loses its contents when the CAT5221 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers (DR) Each potentiometer has four 6-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the Table 3. Instruction Set Instruction Set Instruction Read Wiper Control Register Write Wiper Control Register Read Data Register Write Data Register XFR Data Register to Wiper Control Register XFR Wiper Control Register to Data Register
I3 I2 I1 I0 0 WCR0/ P0 R1 R0
four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 5ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as standard memory locations for system parameters or user preference data. Instructions Four of the nine instructions are three bytes in length. These instructions are: -- Read Wiper Control Register - read the current wiper position of the selected potentiometer in the WCR -- Write Wiper Control Register - change current wiper position in the WCR of the selected potentiometer -- Read Data Register - read the contents of the selected Data Register -- Write Data Register - write a new value to the selected Data Register The basic sequence of the three byte instructions is illustrated in Figure 8. These three-byte instructions
Operation Read the contents of the Wiper Control Register pointed to by P0 Write new value to the Wiper Control Register pointed to by P0 Read the contents of the Data Register pointed to by P0 and R1-R0 Write new value to the Data Register pointed to by P0 and R1-R0 Transfer the contents of the Data Register pointed to by P0 and R1-R0 to its associated Wiper Control Register Transfer the contents of the Wiper Control Register pointed to by P0 to the Data Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of all four pots to their respective Wiper Control Registers Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of all four pots Enable Increment/decrement of the Control Latch pointed to by P0
10010 10100 10110 11000 11010
1/0 1/0 1/0 1/0 1/0
0 0 1/0 1/0 1/0
0 0 1/0 1/0 1/0
11100
1/0
1/0
1/0
Global XFR Data Registers 00010 to Wiper Control Registers Global XFR Wiper Control Registers to Data Register Increment/Decrement Wiper Control Register
Note: 1/0 = data is one or zero
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
0
1/0
1/0
10000 00100
0 1/0
1/0 0
1/0 0
9
Doc. No. MD-2113 Rev. K
CAT5221
exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a maximum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. Four instructions require a two-byte sequence to complete, as illustrated in Figure 7. These instructions transfer data between the host/processor and the CAT5221; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: -- XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. -- XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. -- Global XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. -- Global XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 5 and 9). The Increment/Decrement command is different from the other commands. Once the command is issued and the CAT5221 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SDA 0 1 0 1 A2 A1 A0 Internal Address A I3 C K I2 I1 I0 0 P0 R1 R0 Pot/WCR Register Address Address A C K S T O P
S ID3 ID2 ID1 ID0 A3 T A R Device ID T
Instruction Opcode
Figure 8. Three-Byte Instruction Sequence
SDA 0 1 0 1 A2 A0 A I3 C K Internal Address A1 I2 I1 I0 R1 R0 A C K Pot/WCR Data Address Register Address 0 P0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register D[7:0] A C K S T O P
S ID3 ID2 ID1 ID0 A3 T A Device ID R T
Instruction Opcode
Figure 9. Increment/Decrement Instruction Sequence
SDA S T A R T
0
1
0
1 A3 A2 A1 A0 Internal Address A C K I3 I2 I1 I0 0 P0 R1 R0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P
ID3 ID2 ID1 ID0 Device ID
Instruction Opcode
Pot/WCR Data Address Register Address
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
10
Doc. No. MD-2113 Rev. K
CAT5221
Figure 10. Increment/Decrement Timing Limits
INC/DEC Command Issued SCL
tWRID
SDA
RW
Voltage Out
INSTRUCTION FORMAT Read Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 0 1 0 P0 0 0 A C K DATA 76543210 A C K S T O P
Write Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 1 0 0 P0 0 0 A C K DATA 76543210 A C K S T O P
Read Data Register (DR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 0 1 1 0 P0 R1 R0 A C K AS 76543210CT KO P DATA
Write Data Register (DR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K INSTRUCTION 1 1 0 0 0 P0 R1 R0 A C K AS 76543210CT KO P DATA
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
11
Doc. No. MD-2113 Rev. K
CAT5221
Global Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K A 0 0 0 1 0 0 R1 R0 C K INSTRUCTION S T O P
Global Transfer Wiper Control Register (WCR) to Data Register (DR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K A 1 0 0 0 0 0 R1 R0 C K INSTRUCTION S T O P
Transfer Wiper Control Register (WCR) to Data Register (DR) S T A R T A 0 1 0 1 A3 A2 A1 A0 C K DEVICE ADDRESSES AS 1 1 1 0 0 P0 R1 R0 C T KO P INSTRUCTION
Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T A 0 1 0 1 A3 A2 A1 A0 C K DEVICE ADDRESSES AS 1 1 0 1 0 P0 R1 R0 C T KO P INSTRUCTION
Increment (I)/Decrement (D) Wiper Control Register (WCR) S T A R T A 0 1 0 1 A3 A2 A1 A0 C K DEVICE ADDRESSES INSTRUCTION 0 0 1 0 0 P0 0 0 A C K DATA I/D I/D ... S I/D I/D T O P
Notes: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Doc. No. MD-2113 Rev. K
12
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT5221 PACKAGING OUTLINE DRAWINGS
SOIC 20-Lead 300 mil Wide (W) (1)(2)
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1 E
2.36 0.10 2.05 0.31 0.20 12.60 10.01 7.40 0.25 0.40 0 5
2.49
2.64 0.30 2.55
0.41 0.27 12.80 10.30 7.50 1.27 BSC
0.51 0.33 13.00 10.64 7.60 0.75
c D E E1 e h L
0.81
1.27 8 15
b PIN#1 IDENTIFICATION
e
1
TOP VIEW
D
h
h
1
A
A2
1 END VIEW
A1 SIDE VIEW
L
c
3HFor current Tape and Reel information, download the PDF file from:
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC specification MS-013.
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
13
Doc. No. MD-2113 Rev. K
CAT5221
TSSOP 20-Lead (Y) (1)(2)
b
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1 E
1.20 0.05 0.80 0.19 0.09 6.40 6.30 4.30 0.45 0 6.50 6.40 4.40 0.65 BSC 0.60 1.00 REF 8 0.75 0.15 1.05 0.30 0.20 6.60 6.50 4.50
c D E E1 e L L1 1
e
TOP VIEW
D c A2 A 1 L L1 END VIEW
A1 SIDE VIEW
2HFor current Tape and Reel information, download the PDF file from:
Notes: (1) All dimensions are in millimeters. Angles in degree. (2) Complies with JEDEC specification MO-153.
Doc. No. MD-2113 Rev. K
14
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT5221 EXAMPLE OF ORDERING INFORMATION (1)
Prefix CAT Device # 5221 Suffix W I -10 T1
Optional Company ID Product Number 5221
Temperature Range I = Industrial (-40C to 85C) Package W: SOIC Y: TSSOP Resistance -25: 2.5k -10: 10k -50: 50k -00: 100k
Tape & Reel T: Tape & Reel 1: 1,000/Reel - SOIC 2: 2,000/Reel - TSSOP
ORDERING PART NUMBER
CAT5221WI-25 CAT5221WI-10 CAT5221WI-50 CAT5221WI-00 CAT5221YI-25 CAT5221YI-10 CAT5221YI-50 CAT5221YI-00
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is Matte-Tin. (3) This device used in the above example is a CAT5221WI-10-T1 (SOIC, Industrial Temperature, 10k, Tape & Reel, 1,000/Reel)
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
15
Doc. No. MD-2113 Rev. K
REVISION HISTORY
Date 09/30/2003 10/01/2003 03/10/2004 03/25/2004 04/08/2004 05/23/2007 03/12/2008 Rev. E F G H I J K Reason Deleted WP from Functional Diagram, pg. 1 Changed designation to Advance Added TSSOP package in all areas Updated TSSOP package drawing Eliminated data sheet designation Eliminated Commercial temperature range in all areas Updated Potentiometer Characteristics Updated Example of Ordering Information Added MD- in front of Document No. Updated Package Outline Drawing
Copyrights, Trademarks and Patents (c) Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Adaptive AnalogTM, Beyond MemoryTM, DPPTM, EZDimTM, LDDTM, MiniPotTM, Quad-ModeTM and Quantum Charge ProgrammableTM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. I2CTM is a trademark of Philips Corporation. Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 1Hwww.catsemi.com
Document No: MD-2113 Revision: K Issue date: 03/12/08

▲Up To Search▲

Price & Availability of CAT5221WI-00

	To Download CAT5221WI-00 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .